Memory devices are available in a variety of styles and sizes. Some memory devices are volatile in nature and cannot retain data without an active power supply. A typical volatile memory is a DRAM which includes memory cells formed as capacitors. A charge, or lack of charge, on the capacitors indicate a binary state of data stored in the memory cell. Dynamic memory devices require more effort to retain data than non-volatile memories, but are typically faster to read and write.
Non-volatile memory devices are also available in different configurations. For example, floating gate memory devices are non-volatile memories that use floating gate transistors to store data. The data is written to the memory cells by changing a threshold voltage of the transistor and is retained when the power is removed. The transistors can be erased to restore the threshold voltage of the transistor. The memory may be arranged in erase blocks where all of the memory cells in an erase block are erased at one time. These non-volatile memory devices are commonly referred to as flash memories.
Floating gate memory cells include a source region and a drain region that is laterally spaced apart from the source region to form an intermediate channel region. The source and drain regions are formed in a common horizontal plane of a silicon substrate. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. For example, gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and can also made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is “floating” in dielectric so that it is insulated from both the channel and the control gate.
As cell sizes in memories continue to decrease, and the number of cells associated with memories continues to increase, a larger number of cells are accessed using the same bitline. When a bit is to be read, a high voltage is placed on the bit's word line (control gate) and bitline (drain), and the cell can be read through sensing processes known in the art. Because the channel length of cells is getting shorter, the amount of voltage on the drain side of the channel that is required to start electron injection is also getting smaller. Because the energy of the cells is so high, and the channel length is so short, the electric field on the cells is bigger than it used to be. The electrons injected into the cell by a potential at the drain are hotter and hotter because the channel lengths are getting shorter.
When a cell is being read, then, a voltage at the drain of the cell may actually in some cases begin to soft program the cell. Even if the cell does not fully program due to this effect, fully erased cells become less fully erased, and if enough read cycles pass, the cells may actually begin to read as programmed cells. Even if the cells do not become too programmed to actually read as programmed cells, their margins of erase drop, so that the cells are slower to erase.
Further, because of the architecture of flash memories, and in particular synchronous flash memories, when the memory is moving into a programming cycle from a read cycle, global bitlines are precharged to Vcc or a similar voltage. When all the global bitlines are precharged, and then the word line is turned on for a programming cycle, when the local bitline connection is made to the global bitline, the local bitline sees a voltage of near Vcc. This is sufficient in certain instances to begin to program the particular memory cell by a drain disturb. Cells to be programmed on the local bitline will be overwritten during the programming operation, so there is not a problem with disturbing those cells. However, cells on the bitline that are not being programmed still see the same high voltage when they are coupled to a global bitline precharged to at or near Vcc. Therefore, the unselected cells, that is those cells that are not to be programmed, see a high voltage on their gates, and a drain voltage of near Vcc. With those voltage levels at the gate and source, there is a potential for disturbing the cells.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reducing the drain stress on non-selected cells in a flash memory program operation.